Design and Implementation of an Efficient Reversible Comparator
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Applied Sciences, Free Full-Text
Using new designed NLG gate for the realization of four-bit reversible numerical comparator
Design of Compact Baugh-Wooley Multiplier Using Reversible Logic
Architecture diagram for reversible comparator using half subtraction
Toffoli gate -3*3 gates Download Scientific Diagram
Architecture diagram for reversible comparator using half subtraction
Schematic of 1-Bit comparator using a logic gate
Applied Sciences, Free Full-Text
Optimized design and investigation of novel reversible toffoli and peres gates using QCA techniques - ScienceDirect
Energy-efficient memcapacitor devices for neuromorphic computing
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